A phase-locked loop (PLL), which is also referred to as tracking synchronization below, is used to set a frequency (which has been produced by an oscillator) in such a manner that it matches a reference frequency produced by a reference oscillator. The match must be so accurate that the phase shift between the two frequencies does not drift.
FIG. 1 shows the basic configuration of a phase-locked loop as is known from the prior art. A signal (which has been produced by a reference oscillator 1) at a reference frequency Fref is passed to a 1/R divider 2 which divides the reference frequency Fref by the divisor value R and produces a signal at the frequency Fref′ (which has been divided by R) at the output. A phase detector 3 is used to compare the signal at the frequency Fref′ with a signal at the frequency FVCO′. To this end, the two signals Fref′ and FVCO′ are passed to the phase detector inputs 3.1 and 3.2 of the phase detector 3. At its output 3.3, the phase detector 3 provides an output voltage which is determined by the phase shift between the signal at the frequency FVCO′ (also referred to as the tracking signal below) and the reference signal at the frequency Fref′. A charge pump 4 is connected downstream of the phase detector 3, so that, by means of a control input 4.1 of the charge pump 4, the charge pump 4 can be used to produce a charge pump current Icp at the output 4.2 of the charge pump 4 using the output voltage produced by the phase detector 3. The charge pump current Icp is passed to the input 5.1 of a loop filter 5. The voltage Vtune (also referred to as the tuning voltage below) produced at the output 5.2 of the loop filter 5 is passed to the input 6.1 of a voltage-controlled oscillator 6 in order to set the output frequency FVCO of the voltage-controlled oscillator (VCO) 6. The output signal from the voltage-controlled oscillator 6 at the frequency FVCO is passed, via a feedback path, to a 1/N divider 7 which divides the frequency FVCO to form a frequency FVCO′ (which has been divided by the divisor value N) and, as mentioned, passes it to the input 3.2 of the phase detector 3.
If the frequency FVCO differs from the reference frequency Fref, the phase shift increases in proportion to time. Even in the case of finite control gain, this results in the control error in the closed control loop increasing to such an extent that the two frequencies Fref′ and FVCO′ match exactly. The remaining control error in the frequency thus tends to zero.
If the phase-locked loop PLL is used in a transmitter, a power amplifier 8 may be connected downstream of the output 6.2 of the voltage-controlled oscillator 6 in order to amplify the signal and pass it to an antenna 9. Depending on the application, the 1/N divider 7 may also comprise a radio-frequency initial divider in the form of a fixed-modulus, dual-modulus or multimodulus radio-frequency divider.
The basic configuration of the phase-locked loop shown in FIG. 1 may be used, for example, in a frequency synthesizer.
In this case, a low-frequency, low-noise reference oscillator is first of all needed, as the reference oscillator 1, to produce a radio-frequency carrier frequency FVCO that has as little noise as possible. The 1/R divider 2 (which is referred to as the reference divider below) is used to divide the reference frequency Fref produced by said oscillator to form a lower frequency Fref′, the so-called comparison frequency. The 1/N divider is used to divide the radio-frequency output frequency FVCO of the voltage-controlled oscillator 6 to form the lower frequency FVCO′. The phase difference between the two frequencies Fref′ and FVCO′ is determined using the phase detector 3 and is converted to a signal having a corresponding duty ratio. A pulse-width-modulated signal is then applied to the output 3.3 of the phase detector 3. The charge pump 4 evaluates the duty ratio of the pulse-width-modulated signal and, in conjunction with the loop filter 5, converts the pulse-width-modulated signal to the control voltage Vtune which then controls the voltage-controlled oscillator 6.
The loop filter 5 may be in the form of an active or passive loop filter. In addition, depending on the technical boundary conditions required, the loop filter 5 may be implemented in the form of an integrating or non-integrating loop filter. If the loop filter 5 is in the form of a non-integrating loop filter, only the control difference between the two frequencies Fref′ and FVCO′ is regulated to zero. A phase control error may remain, however. If the phase shift is likewise intended to be minimized, it is advantageous for the loop filter 5 to be in the form of an integrating filter.
In order to implement certain phase-control systems, it may be necessary to interrupt the phase-locked loop in order to produce one or more specific fixed tuning voltages and thus specific fixed VCO frequencies FVCO.
However, interrupting the phase-locked loop, together with producing a fixed VCO frequency, cannot be readily achieved. Intervention upstream or downstream of the loop filter 5 thus results in an additional parasitic load on the circuit. This in turn leads to additional degeneration as regards the phase noise and to an increase in interference lines (which are also referred to as spurious). Modifying the phase detector also results in similar problems.
In principle, it must be ensured, when modifying the phase-locked loop in any way, that the phase noise does not increase by deliberately controlling the edge gradient and restricting the number of circuit blocks used.
In addition, it is important that the various fixed tuning voltages correlate with one another linearly, which is also referred to as matching. If non-linearities were to occur even when producing the various tuning voltages, additional errors would be generated in a circuit which detects and assesses the gradient of the voltage-controlled oscillator.